The PA program was executed in three phases, each of which included at least one major customer demonstration designed to show to a broad audience the emerging capabilities of the system.
Phase 0 was an exploratory phase was conducted by 5 contractors and laid the conceptual groundwork of the subsequent phases. It terminated in 1985 with Demo 1.
Two parallel contracts were awarded for Phase 1 that lasted from early 1986 to late 1989, including Demo 2 in early 1988 and Demo 3 at the end. The aim of Phase 1 was to demonstrate associate functionality without the constraint of having to perform in real time:
The original McDonnell approach was a tightly coupled set of systems running identical rule based engines in lock step. This approach resulted in very slow performance of the system, and was later abandoned in favor of a loosely coupled, federated set of systems.
The Lockheed team approach emphasized selection of the most appropriate implementation for each subsystem, and resulted in a loosely coupled, federated collection of dissimilar systems communicating asynchronously as necessary. Each subsystem of the Lockheed PA was let by a different subcontractor team, and system architecture and integration was under the control of an integration team.
Credit must also be given to two other advisory bodies:
Phase 2 extended from the end of Phase 1 until the middle of 1992, and concluded with the final PA demonstration, Demo 4. Its objective was to demonstrate enhanced (useful) functionality in real-time connected to a full mission simulator. The Lockheed team was the sole contractor for this third phase. Team members in Phase 2 were:
In order to achieve real-time performance, the Lockheed team elected to re-code all of the disparate code demonstrated in Phase 2 in C++ running on a selection of Sun Sparc processors in a VME chassis. Two special-purpose boards were also constructed. One implemented the computationally intensive Route Optimization code. The other provided rapid event management between processors in the chassis to minimize inter-CPU latencies.
last updated 1/26/2003 by David Smith